Mutation Analysis for the Evaluation of Functional Fault Models

Design validation by simulation-based techniques is the most common approach to verification due to the computational complexity of more formal techniques. Validation entails the generation of a test pattern sequence which is applied to the design during simulation to trigger erroneous behavior. Since simulation can only be performed with a small subset of the entire space of test sequences, some method is needed to estimate the degree of verification achieved by a given test sequence. The degree of verification afforded by a test sequence must be known in order to direct test pattern generation, and to provide the designer with the knowledge that verification goals have been achieved.